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MBEL-Computer Organization

MBEL-Computer Organization

Computer Organization

 

Part - A

Q1a): List the type of Instructions. What are the factors that play an important role for selection of instruction set for a machine

Q1b): Why does DMA have priority over the CPU when both request a memory transfer?

Q2a): Describe the role of Encoder & Decoder in Data Transmission. Calculate the size of output data, if Input is given as 4 bits data to Decoder.

Q2b): Calculate the size of Address Code & Op-Code of instruction & draw the Instruction format, if Block size is 512 Bits and No. of operations are 128.

Q3a): Describe the functions of Control Memory in Basic Computer Organization and Design.

Q3b): Describe the each phase of Instruction Cycle used for Micro operation. Give a suitable example to describe Fetch and decode phase of instruction.

Q4: Describe the function of Cache Memory & Virtual Memory in memory organization.

 

Part - B

Case Study

A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory  

Suppose we have the instruction Load 1000. Given that memory and register R1 contains the values tabulated below:

 

Memory Address

Value

1000

1400

---

1100

400

---

1200

1000

---

1300

1100

---

1400

1300

 

Assuming R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator if R1= 200 and fill in the table below:

 

Q1: How many bits are needed for the opcode? How many bits are left for the address part of the instruction?

Q2: What is the maximum allowable size for memory?

Q3: What is the largest unsigned binary number that can be accommodated in one word of memory?

 

Part - C

 

(Note: Mark Bold/Underline for correct answer)

 

Q1: Which memory is faster?

Register

Cache

RAM

Hard disk

 

Q2: Which of the following gates are called universal gates?

AND and OR

AND and NAND

XOR and XNOR

NAND and NOR

 

Q3: The full adder performs binary addition on--

2 binary digits

3 binary digits

2 decimal digits

3 decimal digits

 

Q4: A microprocessor has a data bus with 32 lines and address bus with 20 lines. The

maximum number of bits that can be stored in this memory is

32 x 220

32 x 232

20 x 220

20 x 232

 

Q5: The decimal number +14 can be represented in 6 bit two's complement format as

010010

101110

001110

110010

 

Q6: A reverse polish notation is evaluated with the help of--

Stack

RAM

ROM

None of the above

 

Q7: Pipeline arithmetic units are used to implement--

Floating point operations

Multiplication of fixed-point numbers

A) and B) both

None of the above

 

Q8: In NOR latch, race condition occurs when---

R=0, S=0

R=0, S=1

R=1, S=0

R=1, S=1

 

Q9: A register which can be incremented or decremented and whose primary function is

point to data, is called--

Accumulator

Program Counter

Flat register

Index register

 

Q10: Which of the following is not arithmetic instruction?

MUL

STORE

INC

NEG

 

Q11: The number of fetch operations to execute instruction having immediate operand is--

0

1

2

NON OF THE ABOVE

 

Q12: In instruction cycle--

The indirect cycle is always followed by execute cycle

Fetch cycle is always followed by interrupts

Execute cycle and fetch cycles are simultaneously executed

None of the above

 

Q13: Which of the following gates recognizes only words that have an odd number of 1s?

Nand Gate

Exclusive -OR gate

NOR gate

And Gate

 

Q14: Octal number system is--

A positional system with weights 0 to 9

A positional system with weights 0 to 8

A positional system with weights 0 to 7

A non - positional system with weights 0 to 7

 

Q15: A CPU has a 16 bit program counter. This means that the CPU can address--

16 K memory locations

32 K memory locations

64 K memory locations

256 K memory locations

 

Q16: The sum of two hexadecimal numbers 23D and 9AA gives the hexadecimal number--

AF7

BF6

BE7

BE5

 

Q17: Which of the following memory is not possible?

10 bit address,12 bit cell size, 1024 cells

9 bit address, 8 bit cell size 1024, cells

11 bit address, 8 bit cell size, 1024 cells

10 bit address, 8 bit cell size, 1024 cells

 

Q18: 2's complement of 10101100 is--

1010100

1100010

1001001

1100101

 

Q19: Virtual memory system allows the employment of--

The full address space

More space than the address space

More than the hard disk space

Cache memory

 

Q20: DMA module takes control of bus in order to transfer data when--

Only when the CPU does not need the bus

The data is ready to transfer

Interrupt is being serviced by CPU

None of the above

 

Q21: Pseudo-operation means--

Simulation of arithmetic operations

Directive to assembler to perform a specific operation

Those operations which produce single machine instructions

None of the above

 

Q22: The typical microprocessor is most likely to contain--

ALU

RAM

Power supply

Audio input pin

 

Q23: In register addressing mode operands are looked at--

IN CACHE

In secondary storage

In CPU

In primary memory

 

Q24: The sum of two octal numbers 12 and 17 would be in octal as--

21

23

29

31

 

Q25: The two parts of a microprocessor instruction are called operation and the--

Operator

Operand

Observable

None of the above

 

Q26: . An attempt to execute illegal of undefined instruction may lead to--

TRAP event

I/O interrupt

CPU malfunctioning

None of the above

 

Q27: In karnaugh map of four variables A, B, C and D, the term--

will cover a strip of two squares

will cover a strip of four squares

will cover a strip of three squares

will cover a strip of eight squares

 

Q28: In the memory hierarchy, the fastest memory is--

SRAM

Cache

CPU registers

DRAM

 

Q29: The maximum number of directly addressable location in the memory of a processor having 10 bits wide control bus, 20 bit address bus and 8 -bit data bus is--

1 K

2 K

1 M

2 M

 

Q30: Relocation of program is possible by--

Dynamic programming

Suitably adjusting address sensitive operands in the program

Using appropriate loader

None of these

 

Q31: What can be used to store one or more bits of data, which can accept and/or transfer information serially?

Parallel registers

Shift registers

Counters

None of these

 

Q32: To avoid wastage of memory, the instruction length should be--

Multiple of character size only

Of word size only

Of word size which is multiple of character size

None of these

 

Q33: DMA modules can communicate with CPU through--

Interrupt

Cycle stealing

Branch instruction

None of these

 

Q34: The sequence of microinstructions is also known as--

Software

Hardware

Firmware

None of these

 

Q35: The number of select input lines required for an 8 to 1 multiplexer is--

1K

2K

1M

None of these

 

Q36: A CPU has a 16 bit program counter. This means that the CPU can address--

16 K memory locations

32 K memory locations

64 K memory locations

256 K memory locations

 

Q37: The minimum numbers of bits required to represent numbers in the range -50 to 50 is-

5

7

6

8

 

Q38: Stored program concept may provide--

Maximal use of secondary storage

Program to modify its own instructions

Use of cache memory

None of the above

 

Q39: Viewing computers single addressable memory of unlimited size is connected with concept of --

Virtual memory

Associative memory

Dynamic memory

None of the above

 

Q40: The sum of two hexadecimal numbers 23D and 9AA gives the hexadecimal numbe--r

AF7

BF6

BE7

BE5

 

 

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